The history of the 3nm process technology in chipmaking can be traced to the 1980s. A team of researchers at Nippon Telegraph and Telephone specifically fabricated and demonstrated in 1985 an n-type metal-oxide-semiconductor device with a channel length of 150nm and a gate oxide thickness of 2.5nm. Another team from Advanced Micro Devices fabricated in 1988 a similar device with a channel length of 50nm and gate oxide thickness of 1.3nm.
It was in 2003 when NEC Corporation fabricated the first metal-oxide-semiconductor field-effect-transistor or MOSFET with a channel length of 3nm while Korea Advanced Institute of Science and Technology and the National Nano Fab Center introduced in 2006 a multi-gate MOSFET with a 3nm width based on the gate-all-around or GAFET technology.
The aforementioned were the first attempts at demonstrating and achieving a semiconductor manufacturing process based on the 3nm process node. However, despite the leadership of these companies and research institutions, their semiconductor devices were not commercial products. The commercialization of the 3nm process was pursued by other leading chipmakers such as Samsung Electronics and Taiwan Semiconductor Manufacturing Company or TSMC.
Samsung announced on 25 July 2022 the first shipment of its 3nm gate-all-around chips to the Chinese cryptocurrency mining firm PanSemi. TSMC further announced on 29 December 2022 that the volume production of its 3nm process technology was underway. Marvel Technology released in April 2023 its data center chip based on the 3nm process of TSMC.
Understanding the 3nm Process in Chipmaking and its Advantages and Disadvantages
A process node or a process technology is used in semiconductor fabrication or chipmaking. It is specifically a measurement of the smallest feature size that can be manufactured in the entire semiconductor manufacturing. The measure is described in nanometers and it represents the die shrink or the scaling of metal-oxide-semiconductor field-effect-transistor devices used in electronics and consumer electronics products.
It is important to note that the “nanometer” designation does not represent the physical size of a particular chip. This means that a 3nm chip is not as small as 3 nanometers. It is more of a designation and a marketing label that indicates that the involved semiconductor device was manufactured using the latest-generation manufacturing process or process technology. The 3nm process is an improvement to the 5nm process.
Pros of the 3nm Chips: The Advantages of the 3nm Process Technology
The 3nm process is the successor to the 5nm process that was first introduced for commercial application in October 2020 with the launch of the iPhone 14 that was powered by the A14 Bionic system-on-a-chip from Apple and further with the introduction of its M1 chip in November of the same year. These chips were manufactured by TSMC.
It is important to note that chips based on the 5nm process offered various advantages such as denser transistors, a smaller footprint, performance improvements, and power efficiency. These advantages are further elevated or improved through the 3nm process. The following are the specific advantages of the 3nm process technology:
1. Higher Transistor Density
Semiconductor devices based on this process technology can pack more transistors in the same area than counterparts based on the 5nm process. The transistor density of a particular chip can define its performance. The process technology also allows the design of smaller hardware components, system-on-a-chip with specialized and more advanced components, and more compact or better consumer electronic devices.
2. Performance Improvement
Remember that transistor density can determine the performance or processing capabilities of a particular chip. 3nm chips can achieve 10 to 15 higher performance than 5nm chips at the same power level. This also means that a single integrated chip can have a better-performing central processing unit, integrated graphics processor, and other coprocessors such as image signal processor and AI processor or AI accelerator.
3. Better Energy Efficiency
Another advantage of the 3nm process centers on producing chips that are both powerful and efficient. Estimates have suggested that these chips can use up to 35 percent less power than 5nm chips at the same speed. Remember that 3nm chips can perform better than 5nm chips at the same power level. This advantage translates to more specific benefits. These include improved or longer battery life and lower heat generation.
Cons of 3nm Chips: The Disadvantages of the 3nm Process Technology
The aforementioned advantages of the 3nm process technology translate to the design and production of better semiconductors equipped with improved capabilities and functionalities. This advances further consumer electronics technology. It can also equip specific consumer electronic devices like smartphones and wearables with newer features.
However, despite its promises, it is still important to reiterate the fact that there are variations as regards the implementation of this process technology. There is no single standard as to what constitutes this manufacturing process. This creates performance variations. The following are the specific disadvantages of the 3nm process technology:
1. Manufacturing Challenges
Designing and fabricating semiconductors based on this process technology presents unique challenges compared to older-generation process technologies. These include higher costs from production facilities, advanced lithography techniques, higher energy and other resource requirements, and specific chip designs. These challenges can either limit the scaling benefit of the process or translate to higher end-user pricing.
2. Performance Discrepancies
Another disadvantage of the 3nm process is that there is an absence of a universal standard for its definition and specifications. It is more of a marketing term used to market semiconductors that were fabricated using a newer-generation process technology. This means that the aforesaid advantages would differ across semiconductor devices. Chips based on 5nm or even the older 7nm process could even perform better than 3nm chips.
3. Specific Technical Issues
The process can lead to the design of smaller chips. Take note these chips tend to accumulate unsustainable energy density levels. This can lead to overheating and undesirable consequences. Shortening the gate length of transistors to a single-digit nanometer territory can also influence the behavior of electrons and result in unintended quantum effects such as quantum tunneling, quantum interference, and quantum confinement.
