The A14 Bionic Chip from Apple is the first commercially available system on a chip built using the 5nm manufacturing process node. Based on the ARM architecture, it was announced in October 2020 with the introduction of the iPhone 12 series of smartphones.
However, research on the five-nanometer process stemmed back to the early 2000s. A Japanese research team at NEC Corporation was the first to fabricate a 5nm MOSFET in 2003. Further developments took a considerable time, especially considering that the first 5nm test chips were fabricated in 2015 by Interuniversity Microelectronics Centre and Cadence Design Systems.
Intel Corporation came up with a white paper detailing a lateral gate-all-around FET concept for the 5nm node in 2015, while IBM revealed that they developed the first 5nm silicon chips in 2017 using nanosheets in a gate-all-around configuration.
Samsung Electronics noted in April 2019 that they have been offering tools for the 5nm process now since the fourth quarter of 2018. TSMC also announced in April 2019 that full chip design specifications using their 5nm process were now available to potential customers.
Fast forward to the late 2020s, more chipmakers began introducing chips built on the 5nm manufacturing process. Aside from Apple and its A14 Bionic and Apple M1 chips, the Huawei-owned HiSilicon introduced the Kirin 9000, and Samsung announced the Exynos 1080, both in October 2020, while Qualcomm introduced the flagship Snapdragon 888 in December 2020.
Chips based on the 5nm manufacturing process are poised to become the standard beginning in 2021. Flagship mobile devices such as the Samsung S21 series and the Huawei P50 Pro, as well as the iPhone 12 series and the 2021 iPad Pro, are using 5nm chips.
Pros of 5nm Chips: The Advantages of the 5nm Manufacturing Process
Denser Transistors and Smaller Footprint
One of the advantages of the 5nm manufacturing process is that it allows chipmakers to design and produce chips that have a denser number of transistors in a particular given area, thereby reducing the overall hardware footprint. In other words, when compared with 12nm or 7nm chips, 5nm chips are not only smaller but also have more transistors.
The estimated number of transistors in a 7nm chip is between 95 to 115 million per square millimeter. On the other hand, a 5nm chip can have a transistor density of 125 to 300 million per square millimeter. Of course, these are estimates. The exact numbers or transistor density varies across different chips from different manufacturers.
A prime example is the 5nm Apple M1 chip with a total of 16 billion transistors. For comparison, an Intel Xeon processor based on the 14nm process and introduced in 2017 has about 8 billion transistors while the AMD Ryzen 9 3900X based on the 7nm and 12nm manufacturing processes and released in 2019 has 9.89 billion transistors.
The smaller footprint of 5nm chips also facilitates the design and production of smaller and thinner electronic devices. For integrated chips or systems on a chip, the 5nm process node enables chipmakers to integrate smaller and more advanced chip components such as graphic processing units and artificial intelligence or machine learning processors, among others.
Performance and Power Efficiency Improvements
Chips marketed as “five-nanometer” fundamentally represent the utilization of a new generation of chipmaking process superseding the 12nm and 7nm manufacturing processes. Because they are based on newer engineering and manufacturing technologies and principles, they have better performance and are more power-efficient than the previous generations of chips.
The performance improvements of 5nm chips come from having shorter gate lengths and denser transistors. Having more transistors in a smaller area means faster processing capabilities. Remember that transistors are semiconductors used to amplify or switch electronic signals and electrical power. They are the basic building blocks of modern electronics.
Electrons do not need to travel farther to each transistor in a transistor-dense chip, thereby allowing faster on-off switches and faster processing of information. Chips with denser transistors also deliver a significant improvement in processing performance for the same or a lesser amount of power than those with a lesser number of transistors.
Also, the smaller the distance between the transistor, the lesser power is needed to move an electron from one transistor to another. This is the primary reason why 5nm chips are more power-efficient than older-generation chips. Power efficiency translates to longer battery life, smaller device footprint, or better processing performance using the same amount of energy.
Cons of 5nm Chips: The Disadvantages of the 5nm Manufacturing Process
More of a Commercial or Marketing Term
The term “five-nanometer” or the label “5nm” does not represent the actual physical feature and the related dimension of the transistors, including gate length, metal pitch, or gate pitch. To be specific, it is a marketing term used by chipmakers and their partner manufacturers to represent the new generation of chips designed and manufactured using a new-generation process node.
As mentioned, 5nm chips specifically represent new-generation chips with higher transistor density, better performance, and reduced power consumption or improved power efficiency than 12nm and 7nm chips. However, overall performance improvements across chips using the 5nm manufacturing process are not the same. A 7nm chip can also perform better.
Remember that the “nanometer” label does not exactly indicate the size of individual transistors, the length of space between them, or the dimension of an entire chip. A 5nm chip can also have the same dimension as a 7nm or 12nm chip. The only difference is that the 5nm variant has more transistors. A 5nm chip is essentially an advanced version of a 7nm chip.
It is also important to note that the “nanometer” label attached to a particular chip started to become a mere commercial naming scheme with the introduction of the 250nm chip. Chipmakers encountered a roadblock in 1997 when the size of the specific parts of the transistors failed to keep up with the shrinking size of the gate length.
Challenges of the 5nm Manufacturing Process
Shortening the spaces or gate length between transistors to a single-digit nanometer territory requires using extreme ultraviolet radiation or EUV. But generating EUV alone is a complicated process that involves using sophisticated mirrors and lenses, among others, as well as turning droplets of tin into a glowing plasma using a laser beam.
There is also the need to use smaller wires for interconnection. Several chipmakers have used cobalt instead of copper. This material offers superior resistance and lesser vulnerability at smaller dimensions compared to other materials such as tungsten. However, using cobalt increases further the complexity and cost of the entire chipmaking process.
It is also important to reiterate that the actual manufacturing process nodes used today for newer generations of chips have failed to remain true to the predictions of Moore’s Law due to manufacturing difficulties. Hence, nodes such as the so-called 5nm process node is simply a marketing term based on the previous naming and scaling convention.
A prime example of the ongoing limitations of the entire single-digit nanometer process node is a comparison between different generations of chips. To be specific, the 10nm chips of Intel used foundries that are comparable to 7nm chips. Intel has been having a hard time shortening the gate length despite improvements in transistor density.
Overheating Potentials of Transistor-Dense Chips
Remember that one of the advantages of the 5nm chips is that they are energy efficient. They can have the same or even faster processing capabilities using the same amount of energy than chips based on the 7nm and 12nm process nodes. However, this advantage can also bring forth heating and potential overheating issues.
Smaller chips that consume the same amount of energy as their slightly larger counterparts fundamentally accumulate unsustainable energy density levels, much of these would be dissipated in the form of heat. While this is inevitable, too much heat can affect the performance of the chip while reducing the overall energy efficiency of a particular device.
Too much heat can result in overheating. Note that one of the major causes of overheating in consumer electronic devices is the physical dimension. The dimensions of hardware components and the entirety of a particular device play a role in managing and expelling internally generated heat. Packing transistors in a small area reduces thermal flow.
Overheating can not only affect the performance of a chip but also causes specific hardware damages that can comprise the integrity of an entire device, as well as safety risks. Manufacturing and utilizing 5nm chips based on the 5nm manufacturing process node essentially require taking into consideration different use case scenarios and heat management applications.
FURTHER READINGS AND REFERENCES
- Hiramoto, T. 2019. “Five Nanometre CMOS Technology.” Nature Electronics. 2(12): 557-558. DOI: 1038/s41928-019-0343-x
- Hook, T. B. 2018. “Power and Technology Scaling into the 5 nm Node with Stacked Nanosheets.” Joule. 2(1): 1-4. DOI: 1016/j.joule.2017.10.014
- Schaller, R. R. 1997. “Moore’s Law: Past, Present, and Future.” IEEE Spectrum. 34(6): 52-59. DOI: 1109/6.591665